The invention pertains to the art of 2-D sensing and display arrays and more particularly to a method and applications of forming clusters of pixels in imaging and display arrays.
The invention is applicable to 2-D imaging and display arrays having active matrix configurations using thin film transistors (TFTs) as pixel switches for driving rows and columns of pixels, and will be described with particular reference thereto. It will be appreciated, however, that the invention has broader applications and may be advantageously employed in other environments and applications which may beneficially employ the teachings of the subject invention.
Thin film transistor controlled pixel arrays are the basic building blocks in many types of 2-D image scanners and large area displays. In conventional array designs, a scan driver controls the gate of TFTs to transfer signals to or from each pixel through the data lines. As illustrated in FIG. 1, pixel sensors 10 are arranged in columns and rows to form an array. Each column of pixel sensors 12 share one gate line 14 and each row of pixel sensors 16 share one data line 18. TFTs 20 are located at the juncture of each gate line 14 and data line 18 such that one of the TFTs 20 is connected to a respective pixel sensor/display element 10, gate line 14 and data line 18. Thus, in conventional designs, a pixel configuration 22 is comprised of a gate line, a data line, a pixel sensor/display element and some margins. The width of the gate and data lines are determined by the requirement of conductance to transfer electrical signals. The resolution of an array is limited by both the size of a sensor/display element and the width of the gate and data lines. In order to maintain a reasonable filling factor for imaging or display, the size of the pixel sensor/display element 10 cannot be too small, or the quality of the display or image is affected. If the number of gate or data lines can be reduced, then, the pixel array can be increased in size and performance improved.
In current 2-D image scanners and flat panel displays, each column of pixels connects to external shift registers of high speed single crystalline silicon circuits via a gate line, and each row of pixels connects to external data transferring systems via a data line. In such a design there are numerous line connections between a pixel array and external circuits. Thus packaging is a very complex, difficult and costly undertaking, especially for high density arrays where the pitch between each line is extremely small.
It is also known that with conventional 2-D imaging systems, a significant amount of redundant pixel data are processed. With the array configuration shown in FIG. 1, a sensing process is performed column by column. Every row of data line transfers electrical signals at the same time, and the resolution, gray level, and color of an imaging process are fixed by the design of a particular array, providing little flexibility.
In reality, however, ordinary documents have a variety of resolutions, gray levels, or colors. Even in the same document, different sub-areas may have different image properties (resolution, gray level, or color). Further, depending on an application, different image qualities may be required from the same document. For example, a pre-scan for a high resolution, colored image can be performed with a low resolution and black/white color which may save scanning time and memory space.
Using conventional imaging processes, each pixel in an imaging area reads and sends a signal to a data acquisition system. An external system analyzes the information and then compresses the data. Therefore, a vast amount of transferring and storing of redundant data needs to be processed, resulting in a bottleneck when attempts are made to increase the imaging speed.
Further, in conventional designs N-channel a-Si TFTs with a silicon nitride (SiN) gate insulator have been used as the pixel switches. Such devices are known to have low leakage current, small threshold voltage and excellent switching characteristics. However, P-channel a-Si TFTs, have been known to have lower mobility and poorer switching characteristics. Additionally, for TFTs with a SiN film alone as the gate insulator, the threshold voltage is near 0 volts for N-channel TFTs. Thus, existing conventional array designs implement N-channel TFTs with a single threshold voltage, whereas P-channel TFTs, and TFTs having different threshold voltages have not been considered desirable.
Therefore, it has been determined desirable to develop an imaging and display array where clusters of pixels are formed, and the pixel sensor/display elements within the pixel clusters can be independently addressed. Addressing of the pixel sensor/display elements with the pixel clusters being accomplished by utilizing N-channel and P-channel poly-crystalline Si TFTs with various predetermined threshold voltages. This design allows a connection of more columns and/or rows of pixels to be connected to fewer gate and/or data lines. Such a construction would, (i) reduce the number of data and/or gate lines in an array, improving the filling factor; (ii) reduce the number of line connections to external circuits, simplifying the array packaging process; (iii) allow the selectivity of different resolution levels and imaging patterns for 2-D image scanning, thus improving imaging speed and the reduction of data storage requirements; (iv) allow for simple operation at the pixel level, such as averaging between neighboring pixels by the use of TFTs with various threshold voltages; and, (v) allow for use in color imaging and display due to individual control of pixels used as sub-pixels in a cell unit.